`include "defines.v"
`timescale 1ns / 1ns
module  regs(
    input wire clk,
    input wire rst,
    //from id
    input wire[`RegAddrBus] raddr1_i,
    input wire[`RegAddrBus] raddr2_i,

    //from ex
    input wire[`RegAddrBus] waddr_i,
    input wire[`RegBus] wdata_i,
    input wire we_i,
    //to id
    output reg[`RegBus] rdata1_o,
    output reg[`RegBus] rdata2_o
);

// to construct regs
reg[`RegBus] regs[0:`RegNum - 1];

          
//write the regs
always @(posedge clk)
    begin
        if( rst == `RstDisable && we_i == `WriteEnable)
            begin
                regs[waddr_i] <= wdata_i;
            end 
    end


//to read a data from a specical reg
always @ (*)
    begin
        if (rst == `RstEnable)
            begin
                rdata1_o = `ZeroWord;
            end
        else if (raddr1_i == `RegNumLog2'h0)//if the reg to be read is 0, the data can noly be ZeroWord 
            begin
                rdata1_o = `ZeroWord;
            end
        else if ((we_i == `WriteEnable) && (waddr_i == raddr1_i))
            begin
                rdata1_o = wdata_i;
            end
        else
            begin
                rdata1_o = regs[raddr1_i];
            end

    end

always @ (*)
    begin
        if (rst == `RstEnable)
            begin
                rdata2_o = `ZeroWord;
            end
        else if (raddr2_i == `RegNumLog2'h0)
            begin
                rdata2_o = `ZeroWord;
            end
        else if ((we_i == `WriteEnable) && (waddr_i == raddr2_i))
            begin
                rdata2_o = wdata_i;
            end
        else
            begin
                rdata2_o = regs[raddr2_i];
            end

    end


endmodule
